The packing density of an integrated circuit chip has been continuously raised in the last decade to include millions, or even billions of devices on a single chip. Process technology must therefore be advanced to fabricate integrated circuits with high yield and minimal cost. Thus, some of the most important aspects of semiconductor processing technology, like lithography, etching, deposition, and thermal processing, are being developed aggressively.
Etching plays a vital role in defining prescribed patterns in the semiconductor substrate or subsequent layers. An ideal etching process must transfer the pattern on a masking layer to an underlying layer accurately, and also stop at a predetermined depth. In an anisotropic etching process like a plasma-enhanced etching or reactive ion etching (RIE) process, the pattern on a masking layer is transferred with the least distortion to form an etched region with perpendicular sidewall and expected bottom height.
However, since the etching process removes a target material both chemically and physically, the etching process is very sensitive to a lot of environmental parameters. One of the most challenging factors in traditional etching control is the micro-loading effect. Generally speaking, a semiconductor substrate with a layer to be patterned is subjected to an etching process to define a pattern with a plurality of regions. The regions may be distributed with variant sizes and locations on the chip. The density in the distribution of regions is usually different across the chip or the wafer. Under the chemical and physical reacting mechanism of the etching process, the characteristics of etching are different under the variations of pattern size and density, or namely the variation of "loading".
Referring to FIG. 1a, a schematic top view of a portion of an etching pattern on a semiconductor substrate is illustrated. The shaded area indicates the area to be removed. The pattern may contain several regions with uniform size and density, like regions 10a, 10b, 10c, 12a, 12b, and 12c. The pattern also contains a region 14 for defining a long line. As an example, the pattern can be a contact region pattern for defining contact holes and lines down to an underlying conductive layer. Therefore, the regions are expected to extend down to the same depth reaching an underlying layer. However, because of the loading effect, different pattern regions are etched to different depths.
As shown in FIG. 1b, a cross sectional view of a dielectric layer 16 after the etching process along section line A--A in FIG. 1a. The recessed regions 20 and 22 are respectively formed under the defined regions 10b and 12b. The regions 20 and 22 are formed with the same depth under the uniform dimension and distribution of the defined regions 10a and 12a. However, the recessed region 24 formed under a defined region 14 of extended line area is found to be over-etched with enlarged depth. The non-uniform etching under varied etching loading is called the "micro-loading effect".
With the micro-loading effect, the etching depth of different regions are hard to control. In the example of forming contact holes or lines, a conductive layer 18 underlying the patterned dielectric layer 16 might be damaged under the over-etching of the micro-loading effect. The conductive layer 18 might be broken as shown in FIG. 1b. Besides, other layers underlying the conductive layer 18 can also be damaged under severe over-etching.